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HM-65262
March 1997
16K x 1 Asynchronous CMOS Static RAM
Description
The HM-65262 is a CMOS 16384 x 1-bit Static Random Access Memory manufactured using the Intersil Advanced SAJI V process. The device utilizes asynchronous circuit design for fast cycle times and ease of use. The HM-65262 is available in both JEDEC standard 20 pin, 0.300 inch wide CERDIP and 20 pad CLCC packages, providing high boardlevel packing density. Gated inputs lower standby current, and also eliminate the need for pull-up or pull-down resistors. The HM-65262, a full CMOS RAM, utilizes an array of six transistor (6T) memory cells for the most stable and lowest possible standby supply current over the full military temperature range. In addition to this, the high stability of the 6T RAM cell provides excellent protection against soft errors due to noise and alpha particles. This stability also improves the radiation tolerance of the RAM over that of four transistor (4T) devices.
Features
* Fast Access Time. . . . . . . . . . . . . . . . . . . . 70/85ns Max * Low Standby Current. . . . . . . . . . . . . . . . . . . .50A Max * Low Operating Current . . . . . . . . . . . . . . . . . 50mA Max * Data Retention at 2.0V . . . . . . . . . . . . . . . . . . .20A Max * TTL Compatible Inputs and Outputs * JEDEC Approved Pinout * No Clocks or Strobes Required * Temperature Range . . . . . . . . . . . . . . . +55oC to +125oC * Equal Cycle and Access Time * Single 5V Supply * Gated Inputs-No Pull-Up or Pull-Down Resistors Required
Ordering Information
PACKAGE CERDIP JAN # SMD# CLCC (SMD#) NOTE: 1. Access Time/Data Retention Supply Current. TEMP. RANGE -40oC to +85oC -55oC to +125oC -55oC to +125oC -55oC to +125oC 70ns/20A (NOTE 1) 85ns/20A (NOTE 1) HM1-65262B-9 29109BRA 8413203RA 8413203YA HM1-65262-9 29103BRA 8413201RA 8413201YA (NOTE 1) 85ns/400A PKG. NO. F20.3 F20.3 F20.3 J20.C
Pinouts
HM-65262 (CERDIP) TOP VIEW HM-65262 (CLCC) TOP VIEW
VCC A13 A1 A0 A1 A2 A3 A4 A5 A6 Q W 1 2 3 4 5 6 7 8 9 20 VCC 19 A13 18 A12 17 A11 16 A10 15 A9 14 A8 13 A7 12 D 11 E A2 3 A3 4 A4 5 A5 6 A6 7 Q8 9 10 11 12 GND W E D 2 A0
1 20 19 18 A12 17 A11 16 A10 15 A9 14 A8 13 A7
A0 - A13 E Q D VSS/GND VCC W
Address Input Chip Enable/Power Down Data Out Data In Ground Power (+5) Write Enable
GND 10
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
3002.2
6-1
HM-65262 Functional Diagram
A0 A1 A2 A3 A4 A12 A13
A 7 ROW ROW ADDRESS DECODER 128 MEMORY ARRAY BUFFER A (1 OF 128) 128 X 128 7 128 COLUMN DECODER (1 OF 128) AND I / O CIRCUITRY A 7 A 7 Q
D
E COLUMN ADDRESS BUFFERS W
6-2
A7 A8 A9 A10 A11 A5 A6
HM-65262
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input or Output Voltage Applied for all grades . . . . . -0.3V to VCC +0.3V Typical Derating Factor . . . . . . . . . . . . . . . .5mA/MHz Increase in ICCOP ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
JC Thermal Resistance (Typical) JA CERDIP Package . . . . . . . . . . . . . . . . . . 66oC/W 13oC/W 18oC/W CLCC Package. . . . . . . . . . . . . . . . . . . . 75oC/W Maximum Storage Temperature Range . . . . . . . . . . . . . -65oC to +150oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . +300oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26256 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range HM-65262B-9, HM-65262-9, HM-65262C-9 . . . . .-40oC to +85oC
DC Electrical Specifications
SYMBOL ICCSB1
VCC = 5V 10%; TA = -40oC to +85oC (HM-65262B-9, HM-65262-9, HM-65262C-9) LIMITS
PARAMETER Standby Supply Current
MIN -od -
MAX 50 900 5 50 50 20 400 30 550 +1.0 +1.0 0.8 VCC +0.3 0.4 -
UNITS A A mA mA mA A A A A V A A V V V V V
TEST CONDITIONS HM-65262B-9, HM-65262-9, IO = 0mA, E = VCC -0.3V, VCC = 5.5V HM-65262C-9, IO = 0mA, E = VCC -0.3V, VCC = 5.5V E = 2.2V, IO = 0mA, VCC = 5.5V E = 0.8V, IO = 0mA, VCC = 5.5V E = 0.8V, IO = 0mA, f = 1MHz, VCC = 5.5V HM-65262B-9, HM-65262-9, VCC = 2.0V, E = VCC HM-65262C-9, VCC = 2.0V, E = VCC HM-65262B-9, HM-65262-9, VCC = 3.0V, E = VCC HM-65262C-9, VCC = 3.0V, E = VCC
ICCSB ICCEN ICCOP ICCDR
Standby Supply Current Enabled Supply Current Operating Supply Current (Note 1) Data Retention Supply Current
-
ICCDR1
Data Retention Supply Current
-
VCCDR II IOZ VIL VIH VOL VOH1 VOH2
Data Retention Supply Voltage Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output High Voltage (Note 2) TA = +25oC PARAMETER Input Capacitance (Note 2) Input/Output Capacitance (Note 2)
2.0 -1.0 -1.0 -0.3 2.2 2.4 VCC -0.4
VI = VCC or GND, VCC = 5.5V VIO = VCC or GND, VCC = 5.5V VCC = 4.5V VCC = 5.5V IO = 8.0mA, VCC = 4.5V IO = -4.0mA, VCC = 4.5V IO = -100A, VCC = 4.5V
Capacitance
SYMBOL CI CIO NOTES:
MAX 10 12
UNITS pF pF
TEST CONDITIONS f = 1MHz, All measurements are referenced to device GND
1. Typical derating 5mA/MHz increase in ICCOP. 2. Tested at initial design and after major design changes.
6-3
HM-65262
AC Electrical Specifications VCC = 5V
10%,TA = -40oC to +85oC (HM-65262B-9, HM-65262-9, HM-65262C-9)
LIMITS HM-65262B-9 SYMBOL READ CYCLE (1) (2) (3) (4) (5) (6) (7) TAVAX TAVQV TELQV TELQX Read/Cycle Time Address Access Time Chip Enable Access Time Chip Enable Output Enable Time Chip Disable Output Hold Time Address Invalid Output Hold Time Chip Enable Output Disable Time 70 5 5 5 70 70 30 85 5 5 5 85 85 30 85 5 5 5 85 85 30 ns ns ns ns ns ns ns PARAMETER MIN MAX HM-65262-9 MIN MAX
HM-65262C-9
MIN MAX UNITS
TEST CONDITIONS
(Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 2, 3) (Notes 2, 3) (Notes 2, 3) (Notes 2, 3)
TEHQX
TAXQX TEHQZ
WRITE CYCLE
(8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) TAVAX TELWH TWLWH TAVWL TWHAX TDVWH TWHDX TWLQZ TWHQX TAVWH TAVEL TEHAX TAVEH TELEH TWLEH TDVEH TEHDX Write Cycle Time Chip Selection to End of Write Write Enable Pulse Width Address Setup Time Address Hold Time Data Setup Time Data Hold Time Write Enable Output Disable Time Write Disable Output Enable Time Address Valid to End of Write Address Setup Time Address Hold Time Address Valid to End of Write Enable Pulse Width Write Enable Pulse Setup Time Chip Setup Time Data Hold Time 70 55 40 0 0 30 0 0 55 0 0 55 55 40 30 0 30 85 65 45 0 0 35 0 0 65 0 0 65 65 45 35 0 30 85 65 45 0 0 35 0 0 65 0 0 65 65 45 35 0 30 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
(Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 2, 3) (Notes 2, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3)
NOTES: 1. Input pulse levels: 0 to 3.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate equivalent and CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF. 2. Tested at initial design and after major design changes. 3. VCC = 4.5 and 5.5V.
6-4
HM-65262 Timing Waveforms
A
(3) TELQV E (7) TEHQZ (4) TELQX (5) TEHQX Q
NOTE: 1. W is high for entire cycle and D is ignored. Address is stable by the time E goes low and remains valid until E goes high. FIGURE 1. READ CYCLE 1: CONTROLLED BY E
(1) TAVAX
A (2) TAVQV E (4) TELQX (7) TEHQZ (6) TAXQX Q
NOTE: 1. W is high for the entire cycle and D is ignored. E is stable prior to A becoming valid and after A becomes invalid. FIGURE 2. READ CYCLE 2: CONTROLLED BY ADDRESS
(8) TAVAX A (17) TAVWH (9) TELWH E (11) TAVWL W (12) TWHAX
(7) TEHQZ (10) TWLWH
(13) TDVWH D (15) TWLQZ (4) TELQX Q
(14) TWHDX
(16) TWHQX
NOTE: 1. In this mode, E rises after W. The address must remain stable whenever both E and W are low. FIGURE 3. WRITE CYCLE 1: CONTROLLED BY W (LATE WRITE)
6-5
HM-65262 Timing Waveforms
(Continued)
(8) TAVAX A (20) TAVEH (18) TAVEL E (21) TELEH (19) TEHAX
(22) TWLEH
W (16) TWHQX (23) TDVEH D (24) TEHDX
(4) TELQX Q (15) TWLQZ (7) TEHQZ
NOTE: 1. In this mode, W rises after E. If W falls before E by a time exceeding TWLQZ (Max) TELQX (Min), and rises after E by a time exceeding TEHQZ (Max) TWHQZ (Min), then Q will remain in the high impedance state throughout the cycle. FIGURE 4. WRITE CYCLE 2: CONTROLLED BY E (EARLY WRITE)
Low Voltage Data Retention
Intersil CMOS RAMs are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: 1. Chip Enable (E) must be held high during data retention; within VCC to VCC +0.3V. 2. On RAMs which have selects or output enables (e.g., S, G), one of the selects or output enables should be held in the deselected state to keep the RAM outputs high impedance, minimizing power dissipation. 3. Inputs which are to be held high (e.g., E) must be kept between VCC +0.3V and 70% of VCC during the power up and down transitions. 4. The RAM can begin operation > 55ns after VCC reaches the minimum operating voltage (4.5V).
DATA RETENTION MODE VCC 4.5V VCC 2.0V 4.5V >55ns E VCC -0.3V TO VCC +0.3V
FIGURE 5. DATA RETENTION TIMING
6-6
HM-65262 Typical Performance Curve
VCC = 2.0V -3 -4 -5 LOGIC (ICC/(1A)) -6 -7 -8 -9
-10 -11 -12 -55 -35 -15 5 25 45 65 85 105 125 TA (oC)
FIGURE 6. TYPICAL ICCDR vs TA
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
6-7
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